The Field Programmable Gate Array (FPGA) approach is one of the most recent category, which takes the place in the implementation of most Digital Signal Processing (DSP) applications. It had proved its capability to handle such problems and supports all the necessary needs like scalability, speed, size, cost, and efficiency.
In this paper a new circuit design is implemented for speech scrambling with an implemented example using FPGA is provided. In this implementation the speech coefficients are evaluated on both the scrambled and the De-scrambled sides.
This implementation was achieved using an FPGA Kit after building the logical circuits on the specified kit that uses the Spartan-XL electronic library type implemented using the ISE-4.1 software which is one of the latest versions of the Xilinx Foundation Series 2.1I software.